Processor-Directed Cache Coherence Mechanism – A Performance Study

Cache coherent multiprocessor architecture is widely used in the recent multi-core systems, embedded systems and massively parallel processors. With the ever increasing performance gap between processor and memory, there is a requirement for an optimal cache coherence mechanism in a cache coherent multiprocessor. The conventional directory based cache coherence scheme used in large scale multiprocessors suffers from considerable overhead. To overcome this problem we have developed a compiler assisted, processor directed cache coherence mechanism and evaluated. The approach is autoinvalidation based one that uses a hardware buffer termed Coherence Buffer (CB) and there is no need for directory. The CB method is compared in this paper with a self-invalidation based directory approach that employs a last touch predictor (LTP). Detailed architectural simulations of Distributed Shared Memory configurations with superscalar processors show that 8-entry 4-way associative CB performs better than the LTP based self-invalidation method as well as full-map 3-hop directory for five of the SPLASH-2 benchmarks under release consistency memory model. Given its performance, cost, complexity and scalability advantages, the CB approach is found to be promising approach for emerging applications in large scale multiprocessors, multi-core systems, and transaction processing systems. KeywordsCache coherence, Distributed shared memory multiprocessor system, self-invalidation, Last touch predictor, Release consistency